This is a documentation of my efforts to get a FFT algorithm running on the FPGA in my USRP B100. I started off trying to use an opensource FFT implementation but ended up writing my own, simply because I didn't manage to find an opensource FFT implementation in verilog, with sufficient documentation that I could follow and understand it.

I'll split the documentation into 4 parts:

- Introduction (explain what FFT, FPGA, USRP are).
- Derivation of the decimation-in-time (DIT) FFT algorithm.
- Implementation and of the algorithm in verilog for use on a FPGA.
- Updating the USRP B100 FPGA image to include the FFT.

All the code can be found at https://github.com/benreynwar/fft-dit-fpga and is available under an MIT license.